Found 2 comments on HN
tempguy9999 · 2019-06-04 · Original thread
> Why can't I have fast, low instruction cost communication between any two CPUs, regardless of which core it's on?

Fizzics, specifically a mixture of C and some electrical crap about signal propagation which I don't unnerstand. Einstein, he say no.

> The RISC revolution was in part

true I suppose. Even dumber things were reputed to have been done in the design of the SPARC chips.

> Is it really worth sacrificing an entire cache line to do it?

First show me where this is mentioned in the doc. Second, yeah, why not. If you can pass 512 bits of info between threads in a few cycles, sounds ok to me. If you want another mechanism, be prepared to pay for it. Memory has been around for ages, it's well understood, and bloody fast. It'd be stupid not to use it.

Look, you can't just have stuff cos you want it. You've given no reason for needing it, or that you understand the tradeoffs at the hardware level, or any appreciation of the blinding speed of current chips. How would faster XYZ improve your life?

Go and read < then maybe you'll understand your plaint is falling on uninterested ears (mine anyway). Suggest something constructive based on the realities of hardware then I'll talk.

oso2k · 2014-01-08 · Original thread
I would certainly agree that MIPS, at least as reference architecture, is an very important part of all modern architectures. The Patterson/Hennesey book [1] is absolutely require reading for many Computer Science/Electrical Engineering/Computer Engineering departments (even my state school required it) in undergrad, and most certainly required in graduate school when Computer Architecture turns to pipelining, cache structures and hierarchies, micro-architecture vs. macro-architecture, instruction set design, etc. Without MIPS, there isn't a baseline architecture to talk about in these courses as all other commercial architectures quickly begin to show their biases and optimization strategies.


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