The closest thing I can think of as far as communities would be the http://www.edaboard.com/ folks (although that's a lot of students) or opencores.org (which is more just general projects).

There are a lot more "news" esk hardware design places as well but I'm assuming you're looking closer to stack overflow/github of HDL rather than the slashdot/reddit of HDL?

If you want HDL best practices any of the resources you can get your hands on from http://www.sutherland-hdl.com/papers.html <-- those folks are excellent

and I would highly recommend this book: http://www.amazon.com/SystemVerilog-Verification-Learning-Te...

I haven't gotten a chance to learn UVM yet; is it as awful as VMM? VMM is (arguably) better than nothing, but there's a lot about it that's really broken [1], which can be very frustrating if you're trying to build large-scale exercisers.

If you're interested in the subject, I also recommend reading the book "SystemVerilog for Verification" [2]; it is "the book" on the subject, and although it teaches VMM, it's an excellent reference on the concept of verification to begin with. (It suffers some from the same problem that Kent Beck's Test Driven Development book has -- it verifies excessively simple things -- but IMO, the techniques that it teaches scale much better than Beck's techniques inasmuch as they're actually possible to use in real world applications.)

[1] For instance, for some laughs, take a look at the API reference for the channel datastructure, vmm_channel: http://www.vmmcentral.org/uvm_vmm_ik/files2/vmm_channel-sv.h... -- there is just so much bizarrely wrong that I can't even list it all. "Sneak" is a good place to start, though...

[2] http://www.amazon.com/SystemVerilog-Verification-Learning-Te...