Refer to RISC-V Reader[0].

0. https://www.amazon.com/RISC-V-Reader-Open-Architecture-Atlas...

It depends. For some things, yes. For others, no. This is the best book ever on Risc-V (I think): https://www.amazon.com/RISC-V-Reader-Open-Architecture-Atlas... and they directly compare arm, x86, and risc-v to each other. As you'll see, "it depends".

I can recommend the book The RISC-V Reader: An Open Architecture Atlas by David Patterson and Andrew Waterman.

http://riscvbook.com/

https://www.amazon.com/RISC-V-Reader-Open-Architecture-Atlas...

In the book the authors compare the expressiveness (and thus code density) of code implemented with the RISC-V ISA with instructions for x86, ARM and MIPS. They show that the RISC-V ISA is able to give ARM a good fight in terms of IPC, and that it beats MIPS. (Mainly due to the delay slots which can't be filled in many real world cases.)

They also show why the R5 should make implementations scale better in clock speed compared to ARM. This is the kind of stuff Patterson has been doing research on the last 3-4 decades, and it is quite interesting to see how this experience has guided the design of the RISC-V ISA.